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EL5524, EL5624, EL5724, EL5824
Data Sheet May 23, 2005 FN7346.1
Integrated Buffers with VCOM
The EL5524, EL5624, EL5724, and EL5824 integrate a number of gamma reference buffers with a single VCOM amplifier. The EL5524 contains 4 gamma buffers, the EL5624 contains 6, the EL5724 contains 8, and the EL5824 contains 10. Each gamma buffer has a bandwidth of 12MHz and features a slew rate of 15V/s. The output current is rated at 30mA continuous, 140mA peak. The VCOM amplifiers are rated for 60mA continuous output current and 200mA peak. They also feature higher slew rate and bandwidth for use in error cancellation circuits. The EL5524 is available in the 14-pin HTSSOP package, the EL5624 in the 20-pin HTSSOP package, the EL5724 in the 24-pin HTSSOP package, and the EL5824 in the 28-pin HTSSOP package. All are specified for operation over the -40C to +85C temperature range.
Features
* 4 x gamma buffers (EL5524) * 6 x gamma buffers (EL5624) * 8 x gamma buffers (EL5724) * 10 x gamma buffers (EL5824) * Single VCOM amplifier * 140mA max VCOM output current * Low power - 5.4mA (EL5524) - 6.8mA (EL5624) - 8.3mA (EL5724) - 9.5mA (EL5824) * Pb-Free plus Anneal available (RoHS compliant)
Applications
* TFT-LCD displays * Flat panel monitors * Notebook displays * LCD-TVs
Ordering Information
PART NUMBER EL5524IRE EL5524IRE-T7 EL5524IRE-T13 EL5524IREZ (See Note) EL5524IREZ-T7 (See Note) EL5524IREZ-T13 (See Note) EL5624IRE EL5624IRE-T7 EL5624IRE-T13 EL5624IREZ (See Note) EL5624IREZ-T7 (See Note) EL5624IREZ-T13 (See Note) EL5724IRE EL5724IRE-T7 PACKAGE 14-Pin HTSSOP 14-Pin HTSSOP 14-Pin HTSSOP 14-Pin HTSSOP (Pb-free) 14-Pin HTSSOP (Pb-free) 14-Pin HTSSOP (Pb-free) 20-Pin HTSSOP 20-Pin HTSSOP 20-Pin HTSSOP 20-Pin HTSSOP (Pb-free) 20-Pin HTSSOP (Pb-free) 20-Pin HTSSOP (Pb-free) 24-Pin HTSSOP 24-Pin HTSSOP TAPE & REEL 7" 13" 7" 13" 7" 13" 7" 13" 7" PKG. DWG. # MDP0048 MDP0048 MDP0048 MDP0048 MDP0048 MDP0048 MDP0048 MDP0048 MDP0048 MDP0048 MDP0048 MDP0048 MDP0048 MDP0048
Ordering Information (Continued)
PART NUMBER EL5724IRE-T13 EL5724IREZ (See Note) EL5724IREZ-T7 (See Note) EL5724IREZ-T13 (See Note) EL5824IRE EL5824IRE-T7 EL5824IRE-T13 EL5824IREZ (See Note) EL5824IREZ-T7 (See Note) EL5824IREZ-T13 (See Note) PACKAGE 24-Pin HTSSOP 24-Pin HTSSOP (Pb-free) 24-Pin HTSSOP (Pb-free) 24-Pin HTSSOP (Pb-free) 28-Pin HTSSOP 28-Pin HTSSOP 28-Pin HTSSOP 28-Pin HTSSOP (Pb-free) 28-Pin HTSSOP (Pb-free) 28-Pin HTSSOP (Pb-free) TAPE & REEL 13" 7" 13" 7" 13" 7" 13" PKG. DWG. # MDP0048 MDP0048 MDP0048 MDP0048 MDP0048 MDP0048 MDP0048 MDP0048 MDP0048 MDP0048
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL5524, EL5624, EL5724, EL5824 Pinouts
EL5524 (14-PIN HTSSOP) TOP VIEW
VIN1 1 VIN2 2 VIN3 3 VIN4 4 VS+ 5 VINP 6 VINN 7 THERMAL PAD 14 VOUT1 13 VOUT2 12 VOUT3 11 VOUT4 10 VS9 VOUT 8 NC
EL5624 (20-PIN HTSSOP) TOP VIEW
VIN1 1 VIN2 2 VIN3 3 VIN4 4 VS+ 5 VS+ 6 VIN5 7 VIN6 8 VINP 9 VINN 10 THERMAL PAD 20 VOUT1 19 VOUT2 18 VOUT3 17 VOUT4 16 VS15 VS14 VOUT5 13 VOUT6 12 VOUT 11 NC
EL5724 (24-PIN HTSSOP) TOP VIEW
VIN1 1 VIN2 2 VIN3 3 VIN4 4 VIN5 5 VS+ 6 VS+ 7 VIN6 8 VIN7 9 VIN8 10 VINP 11 VINN 12 THERMAL PAD 24 VOUT1 23 VOUT2 22 VOUT3 21 VOUT4 20 VOUT5 19 VS18 VS17 VOUT6 16 VOUT7 15 VOUT8 14 VOUT 13 NC
EL5824 (28-PIN HTSSOP) TOP VIEW
VIN1 1 VIN2 2 VIN3 3 VIN4 4 VIN5 5 VIN6 6 VS+ 7 VS+ 8 VIN7 9 VIN8 10 VIN9 11 VIN10 12 VINP 13 VINN 14 THERMAL PAD 28 VOUT1 27 VOUT2 26 VOUT3 25 VOUT4 24 VOUT5 23 VOUT6 22 VS21 VS20 VOUT7 19 VOUT8 18 VOUT9 17 VOUT10 16 VOUT 15 NC
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EL5524, EL5624, EL5724, EL5824
Absolute Maximum Ratings (TA = 25C)
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . .+18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V, VS+ +0.5V Maximum Continuous Output Current (Buffer) . . . . . . . . . . . . 30mA Maximum Continuous Output Current (VCOM) . . . . . . . . . . . . 60mA Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS+ = +15V, VS- = 0, RL = 10k, CL = 10pF to 0V, Gain of VCOM = 1, RLVCM = 1k and TA = 25C Unless Otherwise Specified CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
INPUT CHARACTERISTICS (REFERENCE BUFFERS) VOS TCVOS IB RIN CIN AV Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Impedance Input Capacitance Voltage Gain 1V VOUT 14V 0.992 VCM = 0V (Note 1) VCM = 0V 2 5 2 1 1.35 1.008 50 14 mV V/C nA G pF V/V
INPUT CHARACTERISTICS (VCOM AMPLIFIER) VOS TCVOS IB RIN CIN VREG AVOL CMRR Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Impedance Input Capacitance Load Regulation Open Loop Gain Common Rejection Ratio VCOM = 1.5V, -60mA < IL < 60mA RL = 1k -20 55 45 75 70 VCM = 7.5V (Note 1) VCM = 7.5V 1 5 2 1 1.35 +20 50 15 mV V/C nA G pF mV dB dB
OUTPUT CHARACTERISTICS (REFERENCE BUFFERS) VOL VOH ISC Output Swing Low Output Swing High Short Circuit Current IL = 7.5mA IL = 7.5mA RL = 10 14.85 120 50 14.95 140 150 mV V mA
OUTPUT CHARACTERISTICS (VCOM AMPLIFIER) VOL VOH ISC Output Swing Low Output Swing High Short Circuit Current IL = -7.5mA IL = +7.5mA RL = 10 14.85 180 50 14.95 200 150 mV V mA
POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio Reference buffer VS from 4.5V to 15.5V VCOM buffer, VS from 4.5V to 15.5V IS Total Supply Current EL5524 (no load) EL5624 (no load) EL5724 (no load) EL5824 (no load) 55 55 80 80 5.4 6.8 8.3 9.5 7 8.5 11 12.5 dB dB mA mA mA mA
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EL5524, EL5624, EL5724, EL5824
Electrical Specifications
PARAMETER VS+ = +15V, VS- = 0, RL = 10k, CL = 10pF to 0V, Gain of VCOM = 1, RLVCM = 1k and TA = 25C Unless Otherwise Specified (Continued) DESCRIPTION CONDITIONS MIN TYP MAX UNIT
DYNAMIC PERFORMANCE (BUFFER AMPLIFIERS) SR tS BW GBWP PM CS Slew Rate (Note 2) Settling to +0.1% (AV = +1) -3dB Bandwidth Gain-Bandwidth Product Phase Margin Channel Separation -4V VOUT 4V, 20% to 80% (AV = +1), VO = 2V step RL = 10k, CL = 10pF RL = 10k, CL = 10pF RL = 10k, CL = 10pF f = 5MHz 7 15 250 12 8 50 75 V/s ns MHz MHz dB
DYNAMIC PERFORMANCE (VCOM AMPLIFIERS) SR tS BW GBWP PM NOTES: 1. Measured over operating temperature range 2. Slew rate is measured on rising and falling edges Slew Rate (Note 2) Settling to +0.1% (AV = +1) -3dB Bandwidth Gain-Bandwidth Product Phase Margin -4V VOUT 4V, 20% to 80% (AV = +1), VO = 6V step RL = 1k, CL = 2pF RL = 1k, CL = 2pF RL = 1k, CL = 2pF 65 90 150 35 20 50 V/s ns MHz MHz
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EL5524, EL5624, EL5724, EL5824 Pin Descriptions
EL5524 1 2 3 4 5 6 7 8 9 10 11 12 13 14 EL5624 1 2 3 4 5, 6 9 10 11 12 15, 16 17 18 19 20 7 8 14 13 EL5724 1 2 3 4 6, 7 11 12 13 14 18, 19 21 22 23 24 5 8 20 17 9 10 16 15 EL5824 1 2 3 4 7, 8 13 14 15 16 21, 22 25 26 27 28 5 6 24 23 9 10 20 19 11 12 18 17 PIN NAME VIN1 VIN2 VIN3 VIN4 VS+ VINP VINN NC VOUT VSVOUT4 VOUT3 VOUT2 VOUT1 VIN5 VIN6 VOUT5 VOUT6 VIN7 VIN8 VOUT7 VOUT8 VIN9 VIN10 VOUT9 VONT10 Input Input Input Input Positive supply Positive input - VCOM Negative input - VCOM Not connected Output for VCOM Negative supply Output Output Output Output Input Input Output Output Input Input Output Output Input Input Output Output PIN FUNCTION
Test Circuits
VIN
VOUT 10k
VIN
+ 50
VOUT 1k
50
10pF
2pF
FOR BUFFERS
FOR VCOM
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EL5524, EL5624, EL5724, EL5824 Typical Performance Curves
20 NORMALIZED MAGNITUDE (dB) 10 0 -10 -20 -30 100K 150 562 NORMALIZED MAGNITUDE (dB) VS=7.5V CL=10pF 10k 1k 20 10 0 47pF -10 -20 -30 100K 12pF VS=7.5V RL=10k 1000pF 100pF
1M
10M
100M
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE FOR VARIOUS RL (BUFFER)
FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS CL (BUFFER)
100 PSRR+ 80 PSRR (dB) 60 40 20 0 1K PSRR-
600 VS=7.5V OUTPUT IMPEDANCE () 480 360 240 120
VS=7.5V TA=25C
10K
100K FREQUENCY (Hz)
1M
10M
0 100K
1M
10M
100M
FREQUENCY (Hz)
FIGURE 3. PSRR vs FREQUENCY (BUFFER)
FIGURE 4. OUTPUT IMPEDANCE vs FREQUENCY (BUFFER)
80 VOLTAGE NOISE (nV/Hz) 100 OVERSHOOT (%) 70 60 50 40 30 20 10 1 10K 100K 1M FREQUENCY (Hz) 10M 100M 0 10
VS=7.5V RL=10k VIN=100mV
10
100 CAPACITANCE (pF)
1K
FIGURE 5. INPUT NOISE SPECIAL DENSITY vs FREQUENCY (BUFFER)
FIGURE 6. OVERSHOOT vs LOAD CAPACITANCE (BUFFER)
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EL5524, EL5624, EL5724, EL5824 Typical Performance Curves (Continued)
10 8 6 STEP SIZE (V) 4 2 0 -2 -4 -6 -8 -10 200 250 300 350 400 450 500 550 600 650 SETTLING TIME (ns) 0.006 1K 10K FREQUENCY (Hz) 100K VS=7.5V RL=10k CL=12pF THD + NOISE (%) 0.018 0.016 0.014 0.012 0.01 0.008 VS=5V RL=10k VIN=2VP-P
FIGURE 7. SETTLING TIME vs STEP SIZE (BUFFER)
FIGURE 8. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY (BUFFER)
12 NORMALIZED MAGNITUDE (dB) 10 8 VOP-P (V) 6 4 2 VS=5V RL=10k 0 10K
4 2 0 AV=2 -2 -4 AV=10 AV=5 VS=7.5V RL=1k CL=2pF 1M 10M 100M AV=1
100K
1M
10M
-6 100K
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 9. OUTPUT SWING vs FREQUENCY (BUFFER)
FIGURE 10. FREQUENCY RESPONSE (VCOM)
70 50 GAIN (dB) 30 GAIN 10 -10 -30 1K VS=5V RF=1k RL=1k CL=1.5pF 10K 100K 1M 10M PHASE
0 -72 -144 -216 -288 -360 100M PHASE () 0mA 5mA
M=1s/DIV, VS=7.5V, VIN=0V 5mA/DIV RS=0 CL=200pF 0V RS=10 CL=4.7nF RS=10 CL=1nF 500mV/DIV
FREQUENCY (Hz)
FIGURE 11. OPEN LOOP GAIN AND PHASE vs FREQUENCY
FIGURE 12. TRANSIENT LOAD REGULATION - SOURCING (BUFFER)
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EL5524, EL5624, EL5724, EL5824 Typical Performance Curves (Continued)
M=1s/DIV, VS=7.5V, VIN=0V 5mA 0mA RS=10 CL=1nF 0V RS=0 CL=200pF RS=10 CL=4.7nF 500mV/DIV 5mA/DIV 50mA 0mA -50mA VS=7.5V, RL=200, CL=150pF
FIGURE 13. TRANSIENT LOAD REGULATION - SINKING (BUFFER)
FIGURE 14. TRANSIENT LOAD REGULATION (VCOM)
VS=7.5V, RL=10k, CL=12pF
VS=7.5V
50mV/DIV
1V/DIV
200ns/DIV
1s/DIV
FIGURE 15. SMALL SIGNAL TRANSIENT RESPONSE (BUFFER) 1
FIGURE 16. LARGE SIGNAL TRANSIENT RESPONSE (BUFFER)
VS=7.5V, RL=1k, CL=2pF
VS=7.5V, RL=1k, CL=2pF
100mV/DIV
1V/DIV
100ns/DIV
100ns/DIV
FIGURE 17. SMALL SIGNAL TRANSIENT RESPONSE (VCOM)
FIGURE 18. LARGE SIGNAL TRANSIENT REPONSE (VCOM)
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EL5524, EL5624, EL5724, EL5824 Typical Performance Curves (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD HTSSOP EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 3.5 POWER DISSIPATION (W) 833mW 800mW 694mW HTSSOP20 JA=125C/W HTSSOP14 JA=144C/W 0 25 50 75 85 100 125 150 HTSSOP28 JA=110C/W HTSSOP24 JA=120C/W 3 2.5 2.632W 2 1.5 1 0.5 0 0 25 HTSSOP14 JA=38C/W 50 75 85 100 125 150 HTSSOP20 JA=35C/W 3.333W 2.857W 3.030W HTSSOP24 JA=33C/W HTSSOP28 JA=30C/W
1 0.9 POWER DISSIPATION (W) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 909mW
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
Description of Operation and Application Information
Product Description
The EL5524, EL5624, EL5724, and EL5824 are fabricated using a high voltage CMOS process. They exhibit rail to rail input and output capability and have very low power consumption. When driving a load of 10K and 12pF, the buffers have a -3dB bandwidth of 12MHz and exhibit 18V/s slew rate. The VCOM amplifier has a -3dB bandwidth of 35MHz and exhibit 80V/s slew rate.
Choice of Feedback Resistor and Gain Bandwidth Product for VCOM Amplifier
For applications that require a gain of +1, no feedback resistor is required. Just short the output pin to the inverting input pin. For gains greater than +1, the feedback resistor forms a pole with the parasitic capacitance at the inverting input. As this pole becomes smaller, the amplifier's phase margin is reduced. This causes ringing in the time domain and peaking in the frequency domain. Therefore, RF has some maximum value that should not be exceeded for optimum performance. If a large value of RF must be used, a small capacitor in the few Pico farad range in parallel with RF can help to reduce the ringing and peaking at the expense of reducing the bandwidth. As far as the output stage of the amplifier is concerned, the output stage is also a gain stage with the load. RF and RG appear in parallel with RL for gains other than +1. As this combination gets smaller, the bandwidth falls off. Consequently, RF also has a minimum value that should not be exceeded for optimum performance. For gain of +1, RF = 0 is optimum. For the gains other than +1, optimum response is obtained with RF between 1k to 5k. The VCOM amplifier has a gain bandwidth product of 20MHz. For gains 5, its bandwidth can be predicted by the following equation:
Gain x BW = 20MHz
Input, Output, and Supply Voltage Range
The EL5524, EL5624, EL5724, and EL5824 are specified with a single nominal supply voltage from 5V to 15V or a split supply with its total range from 5V to 15V. Correct operation is guaranteed for a supply range from 4.5V to 16.5V. The input common-mode voltage range of the EL5524, EL5624, EL5724, and EL5824 extends 500mV beyond the supply rails. The output swings of the buffers and VCOM amplifier typically extend to within 100mV of the positive and negative supply rails with load currents of 5mA. Decreasing load currents will extend the output voltage even closer to each supply rails.
Output Phase Reversal
The EL5524, EL5624, EL5724, and EL5824 are immune to phase reversal as long as the input voltage is limited from VS- -0.5V to VS+ +0.5V. Although the device's output will not change phase, the input's overvoltage should be avoided. If an input voltage exceeds supply voltage by more than 0.6V, electrostatic protection diode placed in the input stage of the device begin to conduct and overvoltage damage could occur. 9
Output Drive Capability
The EL5524, EL5624, EL5724, and EL5824 do not have internal short-circuit protection circuitry. The buffers will limit the short circuit current to 120mA and the VCOM amplifier
EL5524, EL5624, EL5724, EL5824
will limit the short circuit current to 200mA if the outputs are directly shorted to the positive or the negative supply. If the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. Maximum reliability is maintained if the output continuous current never exceeds 30mA for the buffers and 60mA for the VCOM amplifier. These limits are set by the design of the internal metal interconnections. where: * i = 1 to total number of buffers * VS = Total supply voltage of buffer and VCOM * ISMAX = Total quiescent current * VOUTi = Maximum output voltage of the application * VOUT = Maximum output voltage of VCOM * ILOADi = Load current of buffer * ILA = Load current of VCOM If we set the two PDMAX equations equal to each other, we can solve for the RLOAD's to avoid device overheat. The package power dissipation curves provide a convenient way to see if the device will overheat. The maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature. By using the previous equation, it is a simple matter to see if PDMAX exceeds the device's power derating curves.
The Unused Buffers
It is recommended that any unused buffers should have their inputs tied to ground plane.
Power Dissipation
With the high-output drive capability of the EL5524, EL5624, EL5724, and EL5824, it is possible to exceed the 125C "absolute-maximum junction temperature" under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the buffer to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to:
T JMAX - T AMAX P DMAX = ------------------------------------------- JA
Power Supply Bypassing and Printed Circuit Board Layout
As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible, and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to ground, one 0.1F ceramic capacitor should be placed from the VS+ pin to ground. A 4.7F tantalum capacitor should then be connected from the VS+ pin to ground. One 4.7F capacitor may be used for multiple devices. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. Important Note: The metal plane used for heat sinking of the device is electrically connected to the negative supply potential (VS-). If VS- is tied to ground, the thermal pad can be connected to ground. Otherwise, the thermal pad must be isolated from any other power planes.
where: * TJMAX = Maximum junction temperature * TAMAX = Maximum ambient temperature * JA = Thermal resistance of the package * PDMAX = Maximum power dissipation in the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the loads, or:
P DMAX = V S x I S + i x [ ( V S + - V OUT i ) x I LOAD i ] + ( V S + - V OUT ) x I LA
when sourcing, and:
P DMAX = V S x I S + i x [ ( V OUT i - V S - ) x I LOAD i ] + ( V OUT - V S - ) x I LA
when sinking.
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EL5524, EL5624, EL5724, EL5824 HTSSOP Package Outline Drawing
NOTE: The package drawings shown here may not be the latest versions. For the latest revisions, please refer to the Intersil website at www.intersil.com/design/packages/elantec
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11

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